“Dynamic memory” generally refers to computer memory that retains information stored for only a brief period of time before requiring a “refresh,” wherein a parallel set of bits on a selected row line of the memory is read and then re-written with precisely the same data, unless a write cycle is also initiated during the access cycle. A common example is dynamic random access memory (“DRAM”). “Non-volatile memory” generally refers to computer memory that can retain the stored information when no power is applied and without frequent refreshes. Examples of non-volatile memory include, but are not limited to, mask-programmed read-only memory (“ROM”), field programmable ROM, magnetic RAM, and flash memory.
“Writing” a particular bit into the memory means to drive the bit to a predetermined logic state, also called a data value. In memory capable of storing one of two states, the states may be referred to as “set” and “reset,” commonly referred to as one and zero respectively. “Reading” the state of a particular bit in memory means to determine the state previously written. Reading, writing, or refreshing are generally called “accessing” the memory. Memory may be sequentially accessed, meaning that the stored data must be accessed in a predetermined order, or randomly accessed, meaning that the stored data may be accessed in any order, including sequentially. Examples of non-volatile memory that are sequentially accessed include disk drives and tape drives, and will be referred to herein as “non-volatile storage.” For the remainder of this discussion, “non-volatile memory” will refer to randomly accessible memory (“RAM”), even when such memory supports sequential accesses as an alternative.
Randomly accessible memory is often implemented as a “memory array,” wherein the individual data bits are organized in logical columns and logical rows. A bit of data may be read from the array by examining the state of the bit at the intersection of a particular logical column and a particular logical row. Likewise, a bit may be written by forcing a bit to a pre-selected state. The logical columns and rows constituting the array may be assigned numbers, called addresses, so that each bit or set of bits (e.g. nibble, byte, or word) in the array may be identified by the combination of its column address and row address.
A decoder is an electronic circuit containing combinatorial logic that converts binary information from ‘n’ inputs to 2^n unique outputs. In memory array applications, an address decoder is used to select the row and column lines corresponding to a memory bit to channel the read or write current and voltage to the selected memory cell or cells (e.g. nibble, byte or word). The address decoder operates by converting an ‘n’ bit binary number representing the address of a single bit into a single column line and/or a single row line. In some applications where only a limited portion of the address changes in accessing bits, the address may be refer to a nibble (4 bits), byte (8 bits), word (8, 16, or more bits), or larger sets of bits; accordingly, the address decoder may be designed to select multiple rows, or one or more column lines for a selected row, that correspond to the desired set of bits.
A memory array may be implemented as an integrated circuit, also called a microchip, chip, or die, collectively referring to a miniaturized electronic circuit manufactured on the surface of a thin substrate of semiconductor material. A memory array may also be implemented on a hybrid integrated circuit: a miniaturized electronic circuit constructed of components bonded to a substrate or circuit board or stacked one atop another. Fine wires or leads may be used to interconnect circuit components and the substrate or circuit board. Bonding is the process of connecting together the metal lands on the integrated circuit to the fine wires, pads, or leads used to communicate with other circuit components.
Conductors are used to interconnect circuit elements within an integrated circuit. These conductors may be made of metal, metal alloys, or metal mixtures, all referred to as “metal” or electrodes herein. Other conductive or resistive materials may also be used to interconnect circuit elements, such as, but not limited to, polysilicide.
In a physical manifestation of a memory array on an integrated circuit, conductors addressed as column lines and row lines interconnect the bits and are used to select individual bits in the array. Often, form follows function, and the physical array follows its logical layout: the bits are physically arranged in rows and columns, with column lines and address lines arranged orthogonally. In some cases, however, the physical characteristics of the devices or packing density considerations dictate the physical layout, and the logical relationships are not easily ascertainable by examining the physical layout of the array. In this document, “logical row” and “logical column” denote the arrangement of memory elements as they are addressed, without regard to the actual physical relationship of memory elements. “Row” or “column” may denote either a logical or physical row or column, or both, depending on the context. In DRAM, refreshes are typically performed by selecting a memory row, reading, and the row line may be physically located below, above or adjacent to a column line.
In DRAM, refreshes are typically performed by selecting a memory row, reading all bits on the row in parallel, then re-writing the same data in parallel unless the bits were modified while the row is accessed, all in the same row address cycle. The selection of a memory row and the row address cycle is typically signaled by assertion of a row address select (RAS) signal. Generally, ordinary read and write access must be delayed while a refresh cycle is occurring. This delay is often referred to as “stealing cycles,” and is considered overhead, with less percentage time required for refresh being generally considered as more efficient memory. The refresh cycle may be modified so that data may be read or altered in accordance with a read or write cycle initiated during the refresh cycle; that is, a read or write cycle may serve to refresh a row accessed or a refresh cycle may be used to fetch or read data, so long as each row is accessed within the required refresh specification.
DRAM may be accessed via “page mode,” wherein a single row is selected for a series of accesses made by varying only the column address in either a sequence or to random column addresses within the same row. This technique eliminates delay in re-accessing the row for each successive column address, improving access speed when reading or writing bursts of data on the same row. Depending on the implementation, the length of the access may vary from one or a few bits to all the columns along the entire row. Repeated reads or writes at the same column address may be performed.
A “cache” is often used in computer systems, wherein data stored in a relatively slow form of memory may be copied to a cache for temporary high speed access by a computer. Once data is stored in the cache, future accesses may be directed to the cache rather than to the source of the original data, so that average access time is lower. When data not stored in the cache is requested, the cache data may be written back to the main memory and a new set of data, including data stored at the requested address, is stored in the cache to replace the previously stored data in the cache.
Some DRAM supports “video mode” accesses and is particularly useful to support raster graphics systems. In a raster graphics system, a video memory is called upon to constantly refresh a raster display, and at the same time be responsive to modifications from the host processor. Each host processor access, absent video mode or other external hardware to service the screen, may be held up for repeated cycles, which becomes relatively expensive as overhead, just as stealing cycles for refresh of DRAM increases overhead. While it is possible to update the video memory without external hardware or video mode, it takes a very large portion of the processor capacity, leaving few processor cycles available for other computing tasks and slowing overall performance. Employing video mode memory eliminates this processor demand and reduces overhead load on the processor used to drive the display. Generally, such video memory has two input/output (“I/O”) ports: a port for accesses by a host processor, and a port for accesses by video hardware for driving the display. The video port may support sequential page mode accesses where, for example, 1024 bits in a selected memory row are accessed and loaded in parallel into a shift register. Then, the shift register may be clocked and shifted at the video display speed to refresh a row on the display. In many systems, 8 or more bits per shift may be read from memory and written to the display, with the 8 or more bits providing intensity information, color information, or both. As each row is completed, another row may be loaded from the processor. Video mode may support a format of one or more bits per clock cycle, with one or more parallel output bits on the video port. Some video ports may be read only, and others may be written as the shift register is shifted, and then after shifting through the bits in the row, the row may be reloaded to its position in the memory.
Although video mode accesses are particularly useful for raster graphics systems such as displays for computers, video mode may be useful in many other applications, including printers, cameras, and digital signal processing. Traditional video memories implement with DRAM for main memory have been limited by the requirement to periodically refresh the main memory. Even when the main memory is SRAM that does not require refresh, the main memory must continuously have power to avoid loss of the main memory information.
The purpose of the foregoing Abstract is to enable the public, and especially the scientists, engineers, and practitioners in the art who are not familiar with patent or legal terms or phraseology, to determine quickly from a cursory inspection, the nature and essence of the technical disclosure of the application. The Abstract is neither intended to define the invention of the application, which is measured by the claims, nor is it intended to be limiting as to the scope of the invention in any way.
Still other features of the present invention will become readily apparent to those skilled in this art from the following detailed description. As will be realized, the invention is capable of modification in various obvious respects as will be apparent to those reasonably skilled in the art, and all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative and enabling in nature, and not as restrictive in nature.